1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing thereof. The present invention, in particular, relates to a semiconductor device and a method of manufacturing for promoting miniaturization. Further, the present invention, in particular, relates to a semiconductor device and a method of manufacturing for restraining short circuiting among electrodes and wirings.
2. Related Art
FIG. 6 shows a sectional view of a conventional semiconductor device. This semiconductor device includes a nonvolatile memory (ferroelectric random-access memory, Fe RAM) using a ferroelectric capacitor as a capacitive element and is manufactured by the following method (See Unexamined patent publication 2003-133522), for example.
Firstly, a MOS transistor is formed on a silicon substrate 101. Namely, an element isolation film 102 is formed on the silicon substrate 101 by a LOCOS method and a gate oxide film 103 in the element region located between mutual points of element isolation film 102 is formed by thermal oxidization. Next, polysilicon film is deposited on a region including the gate oxide film 103 and patterned so as to form a gate electrode 104 on the gate oxide film 103. Next, impurity ions are ion-implanted to the silicon substrate with the gate electrode as a mask. Next, a sidewall 105 is formed at the side of the gate electrode 104 and impurity ions are ion-implanted with the sidewall and the gate electrode as masks and a given thermal treatment is completed. Therefore, a low concentration diffusion layer 106 is formed in a lightly doped drain (LDD) region of the silicon substrate 101 and an impurity layer 107 as a source diffused region and a drain diffused region are formed in the source/drain region in the silicon substrate 101.
Next, a first conductive layer, a ferroelectric layer and a second conductive layer are deposited in this order on all surfaces of the MOS transistors and the element isolation layer 102 and patterned so as to form a capacitive element including a lower electrode 110, a ferroelectric material film 111 and an upper electrode 112.
Next, an interlayer insulation film 113 is deposited on all surfaces including the capacitive element and the MOS transistor. Next, a contact bore or hall located on the impurity layer 107 and a contact hall located on the upper electrode 112 are formed on the interlayer insulation film 113. Next, an aluminum alloy film is deposited within the contact hall and on the interlayer insulation film 113 and patterned. Hence, an aluminum alloy wiring 114 connected to the impurity layer 107 and the upper electrode 112 is formed on the interlayer insulation film 113.
In the capacitive element, the upper electrode and the lower electrode require heat resistance so heat resistant metal such as platinum is used. Platinum has high resistance to reaction and corrosion as well as heat resistance. Hence, when the lower electrode, the ferroelectric electrode and the upper electrode are patterned in the same process, etching having physical strength such as ion milling is needed instead of common reactive ion etching (RIE).
However, a taper is easily formed if etching having physical strength is used. Thus, it is difficult to promote miniaturization for a capacitive element. Further, particles are easily formed when etching so that the upper electrode 112 and the lower electrode 110 are short-circuited and the aluminum wiring is also short-circuited. In view of the above situation, the present invention is intended to provide a semiconductor device and a method of manufacturing to promote miniaturization. Further, the present invention is intended to provide a semiconductor device and a method of manufacturing for restraining short circuiting.